(1) Field of the Invention
This invention relates generally to integrated circuits and relates more specifically to generation of reference voltages and currents and their control for integrated circuits.
(2) Description of the Prior Art
Many Analogue, Mixed Signal and even Digital ICs require an internally generated regulated supply rail/s to power their blocks and circuits. The supply voltages for the various internal power domains are normally provided by integrated (on-chip) LDOs (Low Drop-Out Regulators).
Other blocks that are often required for the proper operation of many analogue and mixed-signal ICs are a reference voltage (VREF) Generator—usually a Band Gap based circuit providing an accurate, supply and temperature independent voltage reference, and a IBIAS Generator—providing appropriately scaled bias currents for all analog blocks, and accurate reference currents for ADCs, IDACs, Chargers, Current Comparators and other similar circuits.
The requirement to integrate these three mandatory blocks—internal LDO/s, VREF and IBIAS Generator is particularly relevant to e.g. PM (Power Management) ICs, which typically being the sole PM controller circuit in a system, can not rely on externally generated supply rails or references.
The current practice is to turn on these circuits during the initial power up of the IC and keep them active until the IC is powered down, thus permanently adding their standby current consumption to the overall consumption of the device. This power inefficient approach is particularly disadvantageous for ICs designed for battery operated applications.
The block diagram in FIG. 1A prior art shows a typical configuration of the three core analogue blocks—internal supply regulators such as core low-drop-out regulators (LDO) 1, VREF 2 and (BIAS 3 generators, which have to be integrated on many ICs to ensure their functionality and to guarantee their parametric performance. Also shown are the external passive components that are typically required for the proper operation of these blocks.
Being responsible for the generation of the internal supply voltages, voltage references and bias currents for all other blocks on the chip, these core circuits normally remain active and consume power for as long the IC is powered from the external VDD source. Most of the battery operated mobile devices (phones, MP3 players, GPS navigation, etc.) employ various low power modes (sleep, stand-by, hibernate, etc.) to preserve the battery energy and to maximize the operation time. As a result, the implementation of similar low power modes becomes mandatory also for the integrated circuits used in such applications. An IC in any power saving mode will generally have most (if not all) of the functional blocks powered down (zero current) or in stand-by mode (minimum current), leaving only the core analogue blocks active and ready at any time to quickly bring the chip back into active mode.
Often, when the device is operating in a power saving mode, the total power consumption is dominated by the consumption of the core analogue blocks. This fact highlights the importance of the task of minimizing the power consumption of these circuits. An obvious and commonly used approach is to use ultra-low current designs employing a variety of low voltage and low current architectures. This approach, though, has its own physical and process limitations, i.e. there are certain absolute minimums of the voltage and current levels below which the performance (accuracy, stability, speed, etc.) of the circuit starts being severely affected. In addition, this approach can often be very costly in terms of design time and/or silicon area.
FIG. 1B prior art illustrates the detailed implementation of commonly used circuit architecture for the core analogue blocks. It includes a classical band gap BGAP circuit 4 providing a temperature independent reference voltage and a BGAP BUFFER circuit 5 used to isolate the large external filtering capacitor CF2, and to facilitate the accurate trimming of the VREF voltage. The internal LDO CORE regulator 1 uses the VREF as input voltage reference and generates the internal VLDO supply rail. The VLDO pin is not used as power supply output, but only for connecting the external decoupling capacitor CF1. The BIAS block 3 is powered from the VLDO supply and uses the VREF reference and a precision external resistor RB to generate accurate bias current outputs.
It is a challenge for engineers designing integrated circuits to effectively reduce the power consumption of these core analog blocks.
There are known patents or patent publications dealing with supply sources for integrated circuits:
U.S. Patent Application 2009/0009150 to Arnold discloses an integrated electronic device for generating a reference voltage. The circuitry has a bias current generator for generating a first bias current, a diode element coupled to the bias current generator and fed by a second bias current derived from the first bias current for converting the second bias current into a reference voltage across the diode element, a supply voltage pre-regulator stage for regulating the supply voltage used for the bias current generator, and an output buffer coupled to the reference voltage for providing a low impedance output, wherein the reference voltage is coupled to the supply pre-regulator stage for biasing the supply pre-regulator stage by the reference voltage.
U.S. Pat. No. 7,557,558 to Barrow discloses an IC current reference including a reference voltage Vref, a current mirror, and a transistor connected between the mirror input and a first I/O pin and which is driven by Vref. A resistor external to the IC and having a resistance R1 is coupled to the first I/O pin such that it conducts a current Iref which is proportional to Vref/R1; use of a low TC/VC resistor enables Iref to be an accurate and stable reference current. The current mirror provides currents which are proportional to Iref, at least one of which is provided at a second I/O pin for use external to the IC. One primary application of the reference current is as part of a regulation circuit for a negative supply voltage channel, which can be implemented with the same number of external components and I/O pins as previous designs, while providing superior performance.
U.S. Pat. No. 5,160,856 to Yamaguchi et al. proposes a semiconductor integrated circuit for a CMOS microcomputer and others having an analog circuit, in which a gate voltage of a transistor for setting a bias current is generated by arranging a diode formed by two islands in a MOS structure and a transistor in series, so as to decrease also a temperature dependence characteristic of the analog circuit. Thereby, the fluctuation of the characteristic of the analog circuit can be restrained despite of fluctuation not only of a power-supply voltage but also of a temperature.